1. Field of the Invention
The present invention relates generally to an improved sample-and-hold circuit, and more particularly to reducing sampled noise or inaccuracies in the improved sample-and-hold circuit including therein a compensation circuit portion.
2. Description of the Related Art
In general, a sample-and-hold (“S/H”) circuit samples a voltage value of a signal at a sampling time (the “sample” function), and then outputs a constant voltage corresponding to the sampled value for a period of time thereafter, regardless of whether the sampled signal has subsequently changed (the “hold” function). This is generally accomplished by, at a given sampling time, measuring the voltage of the signal in some way (for example, applying the signal to a capacitor), storing the measurement (for example, the capacitor stores the voltage of the signal applied to it), and then generating an output signal based on the stored measurement (for example, connecting the capacitor that stores the sampled voltage to an input of an amplifier).
For example, FIG. 1 shows the schematics of a S/H circuit 1, which may be referred to as a bottom plate sampling S/H circuit. The S/H circuit 1 comprises an amplifier 10, a sampling capacitor Csamp, and switches SW1, SW2 and SW3. Vref is a reference voltage, and Vin is an input analog signal that is to be sampled. The operation of the S/H circuit 1 will be explained with reference to FIG. 2 through 5.
FIG. 2 shows the timing of the switches during the operation of the S/H circuit 1. In FIG. 2, a high state on any switch means that the switch is closed (i.e. connected), whereas a low state means that the switch is opened (i.e. disconnected). The voltage of the signal Vin is sampled by the S/H circuit 1 during a sampling window comprising time periods t1′ and t2′, and then beginning in time period t3′ the sampled voltage is output as Vout.
Although the theoretically ideal “sample” of a signal is a measure of the value of the signal at a discrete time, in actuality the sample will always be taken over a finite period of time, such as the above-mentioned sampling window spanning periods t1′ and t2′, since all realistic electronic components have finite response times. However, if the sampling period is brief relative to a rate of change of the input signal Vin, the input signal Vin can be assumed to be constant during the sampling window, and the measured value can be assumed to be an instantaneous sample of the signal's voltage at any arbitrary time during the sampling window. Thus, in the example illustrated in FIGS. 2-5, the input signal Vin is assumed to be constant during the sampling window, and the voltage of the input signal Vin during the sampling window will be designated Vin_t1′.
In a first time period t1′, both switches SW1 and SW2 are closed, and SW3 is open. The state of the S/H circuit 1 in period t1′ is shown in FIG. 3 with disconnected paths omitted. In the ideal case, in period t1′ the inverting (negative) input of the amplifier 10 is charged to Vref by the feedback loop through switch SW1; this results in the sampling capacitor Csamp being charged to a voltage of Vc_t1′=Vin_t1′−Vref.
In time period t2, SW1 is opened, which disconnects the feedback path of the amplifier 10. The state of the S/H circuit 1 in time period t2′ is shown in FIG. 4 with disconnected paths omitted. Since there is no path to charge towards the negative plate of the capacitor, the voltage of the sampling capacitor Csamp during time period t2′ remains at the level of the previous stage, i.e. Vin_t1′−Vref.
In time period t3′, SW2 is opened and SW3 is closed, with SW1 remaining open. The state of the S/H circuit 1 in period t3′ is shown in FIG. 5 with disconnected paths omitted. Assuming the input resistance and gain of the amplifier is infinite, the voltage Vc on the sampling capacitor Csamp and the feedback connection on the amplifier cause the output voltage of the amplifier to be the same as Vin. That is:Vout−VcVref=(Vin_t1′−Vref)Vref=Vin_t1′.Thus, as a result of the operations described above, the S/H circuit 1 measures (samples) the voltage of the input signal Vin at a sampling timing (i.e., the voltage Vin_t1′) and thereafter outputs a constant signal Vout corresponding to the measured voltage, i.e. Vout=Vin_t1′.